Semiconductors sit at the absolute foundation of AGI. Every training run, every inference call, every recursive self-improvement loop ultimately bottlenecks on silicon. The AGI buildout is creating the largest sustained demand shock the semiconductor industry has ever seen — dwarfing the PC, smartphone, and cloud eras combined.
Not all sub-sectors benefit equally. GPU/accelerator designers and HBM memory makers face demand that is literally insatiable for the next 2-3 years. Equipment makers and foundries enjoy derivative demand but with longer lead times. Analog, power, and materials companies see real but more moderate tailwinds. This report maps each sub-sector's AGI exposure, supply dynamics, and key investable names.
GPUs and custom AI accelerators (ASICs) perform the massively parallel matrix math that powers training and inference of large neural networks. Modern AI accelerators pack thousands of compute cores alongside high-bandwidth memory interfaces, optimized for the throughput-over-latency tradeoff that deep learning demands. NVIDIA dominates with its CUDA ecosystem, but Google, AMD, and startups compete with custom silicon.
Inference chips are optimized for running trained models at low latency and low power, rather than training them. As AGI-level models get deployed to billions of users and autonomous agents, inference compute will dwarf training compute. Edge inference pushes this into devices — phones, cars, robots — using specialized NPUs (neural processing units) and low-power accelerators.
FPGAs (Field-Programmable Gate Arrays) are reconfigurable chips that can be rewired after manufacturing. They sit between general-purpose CPUs and fixed-function ASICs: more flexible than ASICs but less power-efficient. In AI, they serve niche roles in inference acceleration, network preprocessing, and rapid prototyping of new architectures before committing to full custom silicon.
AI accelerators need massive memory bandwidth to feed their compute cores. HBM (High Bandwidth Memory) stacks multiple DRAM dies vertically with through-silicon vias, delivering 5-10x the bandwidth of standard DRAM. Every NVIDIA H100/B200/Rubin GPU requires multiple HBM stacks. Standard DRAM handles system memory in servers, while NAND flash stores training datasets and model checkpoints.
Foundries manufacture chips designed by others. Every fabless AI chip company (NVIDIA, AMD, Broadcom, Qualcomm) depends on foundries to turn their designs into physical silicon. Leading-edge AI chips require the most advanced process nodes (3nm, 2nm), which only TSMC and Samsung can currently produce at scale. Intel is attempting to re-enter as a foundry.
Lithography tools project circuit patterns onto silicon wafers using light. EUV (extreme ultraviolet) lithography uses 13.5nm wavelength light to print features at 3nm and below. Each EUV machine costs $350M+ and is essentially the most complex machine humanity has ever built. Without lithography, no advanced chips exist.
After lithography patterns a wafer, deposition tools add thin films of materials (metals, insulators, barriers) and etch tools selectively remove material to form 3D circuit structures. Advanced nodes require hundreds of deposition and etch steps per wafer. HBM manufacturing also requires specialized deposition for through-silicon vias and bonding layers.
Inspection and metrology tools find defects and measure critical dimensions on chips during manufacturing. At 3nm and below, a single particle or dimensional error can kill a chip. These tools use electron beams, optical imaging, and X-rays to verify that every layer of every chip meets spec. Yield depends entirely on catching defects early.
Automatic Test Equipment (ATE) validates that finished chips work correctly before they ship. Testers apply electrical signals to chips and check responses against expected patterns. AI accelerators, with their thousands of I/O pins and high-speed interfaces, require sophisticated and expensive test solutions. Testing also ensures HBM stacks and advanced packages meet specs.
Electronic Design Automation (EDA) tools are the software used to design, simulate, and verify chips before they go to manufacturing. No chip — including every AI accelerator — can be built without EDA. These tools handle logic synthesis, place-and-route, timing analysis, power optimization, and physical verification. The EDA market is an effective duopoly (Synopsys + Cadence) with Siemens EDA a distant third.
Semiconductor manufacturing consumes highly pure raw materials: silicon wafers (the substrate), photoresists (light-sensitive chemicals for lithography), specialty gases (for deposition and etching), CMP slurries (for polishing), and various wet chemicals. EUV lithography requires entirely new photoresist chemistries. Materials quality directly determines chip yield.
Analog chips convert real-world signals (voltage, current, temperature, light) into digital data and vice versa. Mixed-signal chips combine analog and digital functions. They handle power management, signal conditioning, sensor interfaces, and data conversion. Every electronic system needs analog chips, but they are not on the critical path for AI compute itself.
AI training clusters require thousands of GPUs working in parallel, connected by ultra-fast networking. Networking chips handle switching, routing, and serialization/deserialization (SerDes) at 400G/800G speeds. InfiniBand and Ethernet-based fabrics move gradients between GPUs during distributed training. Optical transceivers convert electrical signals to light for data center interconnects.
Advanced packaging integrates multiple chiplets, HBM stacks, and interposers into a single package using technologies like CoWoS (Chip-on-Wafer-on-Substrate), InFO, and hybrid bonding. This is how NVIDIA's Blackwell connects two GPU dies with HBM stacks. It extends Moore's Law by combining separately manufactured components rather than shrinking transistors further.
Power semiconductors manage electrical energy: converting, regulating, and distributing power. Silicon carbide (SiC) and gallium nitride (GaN) are wide-bandgap materials that handle higher voltages and temperatures more efficiently than traditional silicon. AI data centers consume enormous power (50-100MW per facility), and every rack needs efficient power delivery from grid to chip.
Each sub-sector is rated on its direct exposure to AGI-driven demand over the next 2-3 years, considering: (1) how directly the sub-sector's products enable AI compute scaling, (2) supply constraint severity and pricing power, (3) concentration of demand among AI-specific customers, and (4) structural barriers to supply response.
Company lists aim for exhaustive US-listed coverage. Some companies appear in multiple sectors (e.g., NVDA in GPU Accelerators and Networking). Tickers are as of May 2026. OTC ADRs are included where they are the primary US trading vehicle for globally significant companies. This report is for research purposes and does not constitute investment advice.