These companies build the machines that turn blank silicon wafers into finished chips. After a lithography tool (made by ASML, not in this group) prints the circuit pattern, deposition tools lay down ultra-thin films of metal and insulator, etch tools carve those films into 3D transistor structures, inspection/metrology tools check that every layer is correct (inspection = finding defects; metrology = measuring dimensions), and test tools confirm the finished chip actually works. Collectively this gear is called WFE (wafer-fab equipment — the production-line machinery inside a chip factory, or "fab"). The four headline US-listed names are Applied Materials (AMAT, deposition + etch + a bit of everything), Lam Research (LRCX, deposition + etch specialist), KLA (KLAC, inspection + metrology leader), and Teradyne (TER, chip testing). The product matters because you cannot expand chip output — the silicon brains of every AI accelerator, HBM (high-bandwidth memory — the stacked memory used next to AI chips) stack, and data-center server — without first installing more of these tools.
Demand for chip-making tools is set to rise as the world builds more fabs and adds extra deposition/etch/inspection steps for advanced packaging and HBM memory — the scan rates AI demand pull "High." Supply here is only moderately constrained: these are oligopolies (a handful of suppliers per segment) with multi-year know-how moats, not a single-vendor monopoly like EUV lithography. So on the scan's own ratings the group is "structurally tight" (oligopoly with elevated backlogs) rather than "acutely sold out" (a single bottleneck vendor). In money terms, these names have generally traded at premium multiples of revenue and earnings versus the broad market est. (arithmetic shown in the price section); the reader judges whether that price fairly captures the future demand-supply gap.
The product is a physical machine — a single deposition or etch tool can cost from a few million to well over ten million dollars est., and a leading-edge fab buys hundreds of them. The unit of demand is the tool (or, aggregated, dollars of WFE spend). The companies earn cash in two layers:
Because the heavy R&D and capital are sunk into designing the tool, each additional machine sold and each year of service tends to carry high gross margin, so cash conversion is strong. These are capital-light businesses relative to the chipmakers they sell to: the chipmaker spends billions on a fab; the equipment maker mostly spends on engineers and earns the margin.
Who buys: a short list of large chip manufacturers — foundries (TSMC), memory makers (Micron, SK Hynix, Samsung), and integrated device makers (Intel). When these customers raise capex, WFE orders rise; when they cut, orders fall. Demand is therefore a derivative of fab construction and node upgrades (a "node" is a generation of chip-manufacturing technology, e.g. 3nm).
Current demand (grounded): the scan rates AI demand pull "High" for deposition/etch and inspection, "Moderate" for test. The stated mechanism is concrete: more fabs mean more equipment orders, and advanced packaging (CoWoS — a TSMC method of placing logic and memory chips side by side on one carrier; and HBM stacking — vertically stacking memory dies) plus 3D structures add incremental deposition, etch, and inspection steps per wafer beyond traditional manufacturing — so tool intensity per chip rises even before unit volume rises.
Forward demand (forecast — AGI lens): given AGI is arriving, compute demand (training and inference) and physical-AI demand (robotics, edge silicon) drive sustained fab build-out and a structural shift toward leading-edge nodes and HBM, both of which are tool-hungry. Two compounding effects: (1) more wafers started, and (2) more tool-steps per wafer at advanced nodes and in packaging. The annual WFE market is roughly $100-120B and has generally been expected to grow at a high-single-digit to low-double-digit annual rate over the medium term, with some forecasts pointing toward roughly $140-150B later this decade. est. These market-size and growth figures are forecasts, not contracted orders.
✓ VERIFIED — the following figures were confirmed from primary sources after initial publication:
Capacity & expansion: unlike a chip fab, tool capacity is expanded mainly by hiring engineers, qualifying suppliers, and scaling assembly — there is no single scarce physical input the way EUV (extreme ultraviolet) lithography depends on ASML's one-of-a-kind optics. The scan rates supply "Moderate" for deposition/etch ("backlogs elevated but not as extreme as ASML") and inspection, and "Mild" for test ("capacity additions are more incremental than building new fabs").
The main bottleneck is know-how and lead time, not raw material or capital. Each new tool generation embeds decades of process physics; a customer that has qualified Lam's etch recipe on a given node will not casually switch vendors, because re-qualifying risks yield (the share of chips on a wafer that come out working). That switching cost — plus long design-in lead times — is what limits the entry of new suppliers, far more than factory space.
Market-share structure (who controls supply): these are oligopolies, segment by segment. est.
Source: 500-stocks scan, /Users/ravf/projects/work/.claude/worktrees/sector-hub/research/investments/500-stocks/02-semiconductors.html (sectors 7-9: Deposition & Etch, Inspection & Metrology, Test).
Putting the two sides together: demand is set to grow (fab build-out + rising tool-intensity per chip under the AGI compute ramp), while supply can expand but is gated by know-how, qualification cycles, and multi-year lead times. On the scan's ratings this is a structurally tight, oligopoly-protected market rather than an acutely sold-out one. The tightening factors are the recurring service revenue and elevated backlogs the leaders carry; the offsetting factor is the scan's "Moderate/Mild" supply rating versus "Extremely" for EUV — i.e. less of a single-vendor chokepoint than lithography.
| Sub-segment | AI demand pull | Supply constraint | Tightness signal |
|---|---|---|---|
| Deposition & Etch | High | Moderate | Elevated backlogs; extra steps from advanced packaging/HBM |
| Inspection & Metrology | High | Moderate | KLA 50%+ share est.; yield-critical at advanced nodes |
| Test (ATE) | Moderate | Mild | Scales more linearly; duopoly capacity adds incrementally |
When could it flip to oversupply? This industry is cyclical: WFE demand follows customer capex, which historically swings in multi-year up/down cycles (memory pricing and macro digestion periods have triggered past downturns). A flip toward oversupply would most plausibly come from a chipmaker capex pause (e.g. a memory glut) rather than from new tool vendors flooding in — entry is hard. So the timing risk is cyclical, distinct from structural change in market share. forecast
| Company (ticker) | What it makes | Exposure to this product | Rough size est. | Position / edge |
|---|---|---|---|---|
| Applied Materials (AMAT) | Deposition, etch, ion implant, some inspection, packaging | Diversified WFE leader — broadest portfolio; not a single-tool pure play | ~$140-180B market cap range est. | Largest WFE company by revenue; widest product spread; large service base |
| Lam Research (LRCX) | Etch & deposition (the purest large play on these two steps) | High purity — etch + deposition are the core; strong memory/3D-NAND exposure | ~$90-130B market cap range est. | Co-leader in etch/deposition; deep recipe lock-in; large installed-base annuity |
| KLA (KLAC) | Inspection & metrology (defect-finding, measurement) | Near pure-play on inspection/metrology | ~$80-110B market cap range est. | Dominant ~50%+ share in its segment est.; among the highest margins in the group |
| Teradyne (TER) | Automatic test equipment (ATE); also industrial automation/robotics | Test is core but TER is also a robotics/automation play — a smaller slice is "pure WFE" | ~$15-25B market cap range est. | Co-leader with Advantest in test; most diversified-away-from-fab of the four |
| Tokyo Electron (TOELY, ADR) | Deposition, etch, coat/develop, cleaning | High — major deposition/etch supplier (Japan-listed; traded here via ADR — a US-listed receipt for a foreign share) | Large-cap (foreign listing) est. | Strong #3 in dep/etch; leads some coat/develop niches |
| Smaller/niche (VECO, ONTO, NVMI, CAMT, COHU, FORM, CVV, IVAC) | Specialty deposition, packaging metrology, test sub-systems | Varies — often single-niche | Small/mid-cap est. | Targeted exposure to specific tool niches; higher idiosyncratic risk (single-name swings not shared across the group) |
Source: company list from the 500-stocks scan (sectors 7-9); market-cap ranges and share figures are general-knowledge estimates, not live-verified.
What does an owner pay today for a dollar of this group's output? Two plain yardsticks:
Money-in / money-out shape: this group is capital-light and cash-generative — the opposite of the chipmakers it sells to. The customers (TSMC, Micron, etc.) spend the tens of billions of capex; the equipment makers collect high-margin systems sales plus a growing recurring service annuity, and convert a large share of profit into free cash (cash left after running and reinvesting in the business), much of which is returned via buybacks and dividends. So the owner cash here comes from margin and the service annuity, not from sinking capital into fabs. The trade-off the price embeds is cyclicality: earnings can swing down hard in a capex pause, so premium multiples coexist with real downside in a downturn. (All multiples above are general-knowledge ranges, not live-verified — confirm against current quotes and the latest filings.)
This is a factual map of where company-level work would be most informative, not a recommendation.