This group sells the software used to design a computer chip before it is ever manufactured. Nothing — no phone processor, no GPU (graphics processing unit, the chip type used for AI training), no custom AI accelerator — gets built without it. The tools handle the whole pre-manufacturing pipeline: turning a chip designer's logic into an actual transistor layout, simulating it, checking timing and power, and verifying it will work before a single (very expensive) wafer (the silicon disc a chip is etched onto) is committed. The category is called EDA (Electronic Design Automation, i.e. chip-design software). By revenue the market is concentrated in a few firms: Synopsys (SNPS) and Cadence (CDNS) together hold the large majority, with Siemens EDA third and Ansys (ANSS, now part of Synopsys) and PDF Solutions (PDFS) in adjacent simulation/analytics niches. The buyers are everyone who designs silicon: Nvidia, AMD, Apple, Qualcomm, and — increasingly — the hyperscalers (the largest cloud operators: Google, Amazon, Meta, Microsoft) building their own AI chips.
The factual setup of this group: demand for chip-design software comes from the number and complexity of chip designs being started, which is rising; supply is the small number of firms able to produce leading-edge tools, which has been stable for years because building a competitive rival suite takes a decade-plus and customers face very high costs to switch tools mid-design. The constraint on "supply" here is not factories or materials but accumulated know-how held by a few firms. Separately, what an owner pays today for exposure is high relative to current cash: these names have historically traded at large multiples of revenue and earnings (see "The price of exposure"). These are descriptions, not a recommendation; the reader judges whether the price is worth it.
The product is a suite of software tools, plus reusable design building-blocks. Think of three things sold together: (1) the design tools themselves — logic synthesis (turning a description of what the chip should do into a circuit), place-and-route (deciding where each transistor physically sits and how they connect), timing/power analysis, and verification (proving the chip works before manufacturing); (2) IP blocks (intellectual-property blocks — pre-designed, pre-verified circuit components like memory controllers or interface ports that a customer drops into their own chip instead of designing from scratch); and (3) simulation/analysis software for the physical behaviour of the chip and the system around it (heat, stress, signal integrity).
The unit it is sold in is a seat (one engineer's licence to use the tool) and, more broadly, a design start (each new chip project a customer begins). More chip projects, and more engineers on each project, means more seats and more IP licences. The cash mostly arrives as multi-year software contracts. A large share of revenue is recurring (the customer renews every year because switching tools mid-design is extremely costly), which is why these companies talk about RPO (remaining performance obligation — contracted future revenue already signed but not yet recognised as a sale). In plain money terms: a customer signs a multi-year licence, pays roughly steadily over the term, and the vendor recognises that as revenue over time. Because the cost to serve one more customer is mostly already-written software, a high fraction of each incremental sale becomes operating profit.
Source: 500-stocks semiconductors scan, "EDA & Design Software" sub-section (/Users/ravf/projects/work/.claude/worktrees/sector-hub/research/investments/500-stocks/02-semiconductors.html), plus general industry knowledge.
Demand is driven by one simple thing: the number of chip designs being started, and how complex each one is. Both are rising. The scan's own read is blunt: the AI demand driver is "strong and compounding" — more AI chip designs means more EDA licences, and "every hyperscaler designing custom AI silicon (Google, Amazon, Meta, Microsoft) is a new EDA customer."
Who the buyers are. Traditional chip companies (Nvidia, AMD, Intel, Qualcomm, Apple, Broadcom), the new custom-silicon programs at the hyperscalers, the foundries (the factories that manufacture chips — TSMC, Samsung, Intel) who co-develop tool flows for each new manufacturing node (each generation of smaller, denser transistors), and a long tail of startups designing specialised AI and edge chips.
Current demand. The installed base is the entire semiconductor design industry — essentially every company that makes a chip is already a customer of the leading vendors. Revenue here is well into the tens of billions of dollars combined across the group annually, and a large slice is contracted (recurring licences + signed backlog) rather than hoped-for. contracted
Forward demand (forecast). Reasoning from the premise that AGI is arriving, the number of distinct silicon designs should grow structurally, not just cyclically: (a) compute demand keeps pulling new accelerator generations forward on a faster cadence; (b) physical AI — robotics, autonomous systems, edge inference (running AI on local devices rather than in the cloud) — multiplies the variety of chips being designed; (c) each new manufacturing node is harder, so each design consumes more tool-hours and more engineers (more seats per design); and (d) AI is now being embedded inside the EDA tools themselves, which both raises the value the vendor can charge for and lets customers run more design experiments (more compute used = more tool consumption). The scan flags this last point as a "virtuous cycle." These are forecasts, not contracted facts. forecast
✓ VERIFIED — the following figures were confirmed from primary sources after initial publication:
This is the key difference from the rest of the AI build-out: there is no physical capacity limit. Software can be copied infinitely. So "supply" does not mean factories, wafers, or megawatts — it means who is capable of producing tools good enough to design a leading-edge chip. On that definition, supply is extremely constrained, and the scan says so directly: it is "not [constrained] in the physical sense, but intellectual moats are enormous. It takes decades to build competitive EDA software. Switching costs are near-infinite. This is a toll-booth business on all semiconductor innovation."
The real bottleneck is know-how plus lock-in. A credible EDA suite is decades of accumulated software, tightly co-engineered with each foundry's manufacturing process. A customer that has built a chip on one vendor's flow cannot cheaply re-verify it on another's mid-project, so they renew. That combination — deep technical moat plus very high switching costs — means new supply (a new credible competitor) is unlikely to appear on any near-term horizon. The constraint is human/engineering capital and time, not capital spending.
Market-share structure (who controls supply). A small number of firms: Synopsys and Cadence together hold the large majority, Siemens EDA is third, and Ansys (now combined with Synopsys) and PDF Solutions sit in adjacent simulation/analytics niches. est. Because the constraint is know-how rather than buildable capacity, the share structure has been unusually stable — there is no mechanism for a sudden capacity flood the way there is in a physical-goods market.
Source: 500-stocks semiconductors scan, "EDA & Design Software" sub-section; market-share estimates from general knowledge (not live-verified).
Put together: demand (chip designs and seats) is rising structurally, while supply (credible toolmakers) has stayed at roughly two-to-three firms because of a deep know-how moat. The product is therefore "short" in the economically meaningful sense — buyers cannot easily route around the leading vendors, so the imbalance shows up as pricing power and high renewal rates rather than as shortages of physical units.
The evidence of tightness is different from a commodity. There is no spot price spiking and no sold-out factory. Instead the signs are: (1) high and sticky recurring revenue with strong renewals; (2) growing signed backlog (RPO — contracted future revenue); (3) steady price/value escalation as each new node and each AI feature lets the vendor charge more per seat; and (4) the absence of any new entrant despite obvious incentive.
| Factor | Demand side | Supply side |
|---|---|---|
| Direction | Rising (more designs, more seats, AI inside tools) | Flat number of credible producers |
| What sets the limit | Number/complexity of chip design starts | Decades of know-how + very high switching costs |
| Can the limit be relieved fast? | n/a (demand pull) | No — years to build a rival |
| Tightness signal | High renewal, growing backlog (RPO) | No new entrants despite incentive |
| When could it flip to oversupply? | No physical oversupply mechanism exists. The realistic risks are not "too much supply" but: a cyclical pause in chip design spending, or a future where AI itself collapses design effort so fewer seats are needed per chip. Both are speculative. forecast | |
Note the one genuine two-sided risk to this group: AI inside the tools is currently a tailwind (vendors charge more), but if design automation eventually becomes good enough that far fewer engineer-seats are needed per chip, the "seat" unit of demand could shrink even as the number of chips rises. Which effect dominates is unknown. forecast
| Company | What it makes | Exposure to EDA | Rough size | Position / role |
|---|---|---|---|---|
| Synopsys (SNPS) | Full EDA design+verification suite, plus the largest IP block library; now also Ansys simulation | Near pure-play (vast majority of revenue) est. | Mega-cap; tens of $B market cap est. | Co-leader by revenue; large design-IP business; broadened into multiphysics simulation via Ansys |
| Cadence (CDNS) | EDA design+verification suite, system-design/analysis tools, growing IP | Near pure-play (vast majority of revenue) est. | Mega-cap; tens of $B market cap est. | Co-leader by revenue; strong in custom/analog design and verification |
| Ansys (ANSS) | Engineering simulation (structural, fluids, electromagnetics, multiphysics) | Adjacent simulation, not core EDA; combined into Synopsys | Large-cap (now part of SNPS) est. | Simulation leader; the "physics" layer being combined with EDA |
| PDF Solutions (PDFS) | Manufacturing/yield analytics and data systems for fabs | Adjacent analytics niche, not core design tools | Small-cap est. | Niche specialist in yield/data; not a core-design-tools competitor |
| Siemens EDA | Full EDA suite (formerly Mentor Graphics) | Part of Siemens — a small slice of a large industrial conglomerate | Inside Siemens (not a US-listed pure-play) | Third by revenue; not available as a standalone US-listed EDA stock |
Source: company list from the 500-stocks semiconductors scan; relative sizes and shares from general knowledge (approximate, not live-verified). Confirm current market caps, the Ansys deal status, and segment revenue mixes against the latest filings before relying on them.
The money-in/money-out shape here is the opposite of the rest of the AI build-out. EDA is capital-light: the companies spend on engineers (R&D), not on factories, so very little of each dollar of revenue is consumed by capex (capital expenditure — money spent on physical plant and equipment). That means a high fraction of revenue converts to operating profit and to owner cash (free cash flow — the cash left after running and reinvesting in the business). On the reported numbers these are cash generators rather than cash-burners.
The trade-off is the price paid for that profile. The leaders have historically traded at high multiples of both revenue and earnings — roughly on the order of $10+ of market value per $1 of annual revenue, and a P/E (price-to-earnings — market value per $1 of annual profit) well into the tens, often higher than the broad-market average. est. In plain money terms, at those multiples an owner pays up front and recovers current revenue/earnings only slowly, with the rest of the price riding on future growth — i.e. the price reflects years of the demand-over-supply gap described above. Whether that price is worth it is the reader's judgment; no view is stated here.
Source: valuation magnitudes from general knowledge (approximate, not live-verified). Pull current price, share count, revenue, and free cash flow from the latest 10-Q/10-K before using any specific multiple.
This is a factual map of where to look, not a recommendation on any name.
Source: /Users/ravf/projects/work/.claude/worktrees/sector-hub/research/investments/500-stocks/02-semiconductors.html (sub-section "EDA & Design Software"); general industry knowledge (cutoff ~early 2026, not live-verified).