A foundry is a factory that builds the physical chips that other companies design. NVIDIA, AMD, Apple, Broadcom, Google and Amazon draw the blueprints (they are "fabless" — they own no fabs); the foundry turns those blueprints into actual silicon. The unit being sold is a wafer — a thin disc of silicon, about 300mm (12 inches) across, on which hundreds of chips are printed at once. The product this group sells is "advanced-node" wafer capacity: the most cutting-edge manufacturing (today the 3-nanometre and 2-nanometre generations, where "nanometre"/"nm" is a marketing label for how small and dense the transistors are). Every leading AI accelerator (the specialised chip that runs AI training and inference) on the market is built on this handful of production lines, so this group is the physical chokepoint of the entire AI/AGI build-out.
At the leading edge, demand currently runs ahead of supply: AI customers book the most advanced capacity years in advance and it routinely sells out. What limits supply is not silicon but capital, time and know-how — a fab costs $20-40B and takes 3-4 years, and within the fab the tightest single bottleneck is "advanced packaging" (CoWoS), the step that stitches the logic chip to its memory. In money terms, the leading name (TSMC) trades at a higher multiple of revenue and earnings than the lagging-edge names (UMC, GlobalFoundries) and the re-entry case (Intel) est. — the specific multiples are laid out in the price section below for the reader to weigh. No recommendation is implied.
Source: 500-stocks scan — Semiconductors, sub-sector 5 "Foundries (Contract Chip Manufacturing)"; plus general-knowledge figures labelled est.
The product is contract chip manufacturing: a customer brings a finished design, the foundry prints it onto silicon wafers in a fab (fabrication plant), and ships the wafers back (often after testing and packaging). The customer owns the design and the resulting chips; the foundry owns the factory and the process recipe. This is why it is called "pure-play" foundry — the foundry does not compete with its own customers by selling chips under its own brand.
Money is made three ways, all of which a non-finance reader can picture as renting an extremely expensive printing press:
The economics are heavily capital-intensive. "Capex" (capital expenditure — cash spent building factories and buying machines) runs into the tens of billions per year for the leaders. The owner's payoff is "gross margin" (revenue left after the direct cost of making each wafer) and, after capex, "free cash flow" (the cash actually left over for the owner once the factories and machines are paid for). TSMC has historically run gross margins in roughly the 50-55% range est.; lagging-edge players have run thinner margins est..
Source: 500-stocks scan sub-sector 5; wafer pricing and margin levels are general-knowledge est., not live-verified.
Demand for advanced-node wafers is, in the scan's own words, "enormous." Every fabless AI chip company — NVIDIA, AMD, Broadcom, Qualcomm, plus the in-house chips from Google, Amazon, Microsoft and Meta — depends entirely on foundries to turn designs into silicon. There is no second path: if you want a modern AI accelerator physically built, you are in line at TSMC (and to a lesser extent Samsung).
Current demand (known facts): The scan states that AI-related revenue at the leading foundry is "growing 3x faster than its overall business," and that AI chips already "consume a large and growing share of leading-edge wafer capacity." TSMC's total revenue is roughly $90-100B a year est., of which the high-performance-computing/AI segment is the fastest-growing piece. Advanced nodes (5nm and below) make up the majority of TSMC's revenue today est..
Forward demand (forecast — given AGI is arriving): If recursive self-improvement and broad AI deployment proceed, the demand driver is not one product cycle but a sustained, compounding need for compute. Each generation of frontier model, each new inference workload, and the coming wave of physical AI (robots, autonomous systems) all ultimately bottleneck on leading-edge silicon. Industry forecasts put AI accelerator demand growth in the high-double-digit to triple-digit percent range over the next few years est. — and because each accelerator consumes leading-edge wafers plus advanced packaging, that demand lands directly on this group. The relevant question for an owner is less "will demand grow" and more "can supply physically keep up" — addressed in the next section. These growth figures are forecasts, not contracted orders.
Who the buyers are: a concentrated set of very large, well-funded customers. The same hyperscalers (the largest cloud operators — Google, Amazon, Microsoft, Meta) and AI-chip designers buying GPUs are the ultimate source of foundry demand. That concentration cuts both ways: it makes near-term demand visible and bankable, but it means a slowdown in AI capex by a few giant buyers would be felt quickly.
✓ VERIFIED — the following figures were confirmed from primary sources after initial publication:
Source: 500-stocks scan sub-sector 5 (AI demand driver, "3x faster" growth note); forward growth and revenue figures are general-knowledge est.
Supply is the whole story for this group, because it is genuinely hard to add. The scan is explicit: leading-edge capacity "is allocated years ahead," a new fab "costs $20-40B and takes 3-4 years," and advanced packaging (CoWoS) "is the tightest bottleneck within foundries."
Current capacity & expansion (known/announced): TSMC is the dominant supplier of leading-edge capacity and is spending in the range of $40B+ a year on capex est., building new fabs in Taiwan and overseas (Arizona, Japan, planned Europe). Samsung is the only other company shipping leading-edge logic at scale, though at lower volume and yield. Intel is spending heavily to re-enter as a foundry (Intel Foundry) on its 18A/14A roadmap but is not yet a proven high-volume external supplier. GlobalFoundries and UMC deliberately do NOT chase the leading edge — they specialise in mature/specialty nodes (older, cheaper, very reliable processes used for analog, power, RF and automotive chips).
The real bottleneck is a stack of hard-to-replicate inputs, in roughly this order:
Market-share structure (who controls supply): highly concentrated. TSMC holds roughly two-thirds of the total foundry market and the large majority — about 90%+ — of leading-edge output est.. Samsung is a distant second at the leading edge; the rest of the market (UMC, GlobalFoundries, SMIC and others) sits almost entirely at mature nodes. So "supply of the AI-relevant product" is, in practice, mostly one company's decision.
Source: 500-stocks scan sub-sector 5 (fab cost, lead time, CoWoS bottleneck, "allocated years ahead") and sub-sector 6 (ASML/EUV monopoly, ~50-60 systems/yr); share and capex figures are general-knowledge est.
Putting the two together: at the leading edge the product is structurally short — more buyers than wafers — and has been for the duration of the AI build-out. The evidence is qualitative but consistent across the scan: capacity "allocated years ahead," advanced packaging sold out, AI revenue growing 3x the rest of the business, and rising wafer prices on new nodes. At the lagging/mature edge the picture is more balanced-to-soft: that capacity is plentiful, prices are competitive, and utilization swings with the broader (non-AI) electronics cycle.
| Signal | Leading edge (3nm/2nm + CoWoS) | Mature / specialty nodes |
|---|---|---|
| Pricing trend | Up est. | Flat / competitive est. |
| Capacity status | Sold out, booked years ahead | Ample, cycle-dependent |
| Utilization | Near full est. | Variable est. |
| Lead time to add supply | 3-4 yrs + ASML/CoWoS limits | Shorter, less constrained |
| Demand driver | AI/AGI compute | Auto, industrial, consumer |
| Short or long? | Short | Balanced / cyclical |
When could it flip to oversupply? Two paths, both forecasts. (1) Supply catches up: the industry's announced fab build-out (TSMC, Samsung, Intel, plus government-subsidised fabs) is large; if all of it comes online on schedule into a demand pause, leading-edge could loosen 2-3 years out. Historically the foundry business is cyclical and has had periods of oversupply. (2) Demand stalls: because the buyer base is concentrated, a pullback in AI capex by a few hyperscalers would cut demand quickly. Under the AGI-arriving premise, sustained compute demand argues against a near-term glut at the leading edge — but the lead time on supply cuts both ways, and the reader should treat the timing of any flip as unknown, not contracted.
Source: 500-stocks scan sub-sector 5; pricing/utilization arrows are general-knowledge est.; oversupply timing is forecast.
The five US-listed names from the scan fall into three buckets: the leading-edge leader, the would-be challengers, and the mature-node specialists. Figures below are approximate and not live-verified.
| Company (ticker) | What it makes | Exposure to advanced-node AI wafers | Rough size | Position / edge |
|---|---|---|---|---|
| TSMC (TSM) | Pure-play foundry, all nodes incl. 3nm/2nm + CoWoS packaging | Very high — the dominant AI-wafer supplier | ~$90-100B rev/yr; ~$0.9-1T+ mkt cap est. | ~90%+ leading-edge share; leading yields; CoWoS owner est. |
| Samsung (SSNLF, OTC ADR) | Conglomerate: memory + leading-edge logic foundry + consumer | Moderate — only other leading-edge maker, smaller share | Very large but foundry is a slice est. | #2 at leading edge; yield gap vs TSMC est. |
| Intel (INTC) | Own-brand CPUs + Intel Foundry (18A/14A) trying to take external orders | Aspirational — building, not yet proven at volume | ~$50B+ rev/yr (mostly products) est. | Re-entry attempt; heavy capex; US-onshore footprint |
| GlobalFoundries (GFS) | Pure-play foundry at MATURE/specialty nodes (no leading edge) | Low to AI accelerators; serves auto/IoT/RF | ~$6-8B rev/yr est. | Specialty/differentiated mature processes; US/EU footprint |
| UMC (UMC) | Pure-play foundry at MATURE nodes (no leading edge) | Low to AI accelerators; broad mature-node customer base | ~$7-8B rev/yr est. | Scale mature-node player; cost-competitive |
The key bridge for a deep-dive: only TSMC (and partly Samsung) is a direct play on the AI-wafer shortage. Intel is a bet on a re-entry succeeding. GFS and UMC are cash-generating foundries but they are NOT exposed to the leading-edge AI gap — they ride the broader chip cycle. This describes their exposure, not a view on which is the better holding.
Source: 500-stocks scan sub-sector 5 company list (TSM, INTC, GFS, SSNLF, UMC); revenue and market-cap figures are general-knowledge est., not live-verified.
In plain money terms, what does an owner pay today for $1 of these companies' annual revenue, and how much owner cash does that revenue actually throw off? The two questions matter together because a foundry can have large revenue and still hand little to the owner if capex eats it. All figures below are approximate and not live-verified.
The money-in / money-out shape of the group: this is one of the most capital-intensive businesses in the economy. Money goes in as large, multi-year capex on fabs and machines BEFORE any wafer ships; money comes out later as high-margin wafer sales IF the fab fills up. The leading edge (TSMC) has historically spent ~$40B/yr and still returned cash to owners est.; the challenger (Intel) is in the spending-ahead phase; the mature players (GFS, UMC) run a lower-stakes, lower-return version of the same machine. The arithmetic for the reader: a higher price-to-revenue multiple corresponds to the scarce, cash-generative leading-edge asset; a lower multiple corresponds to either a re-entry bet or a cyclical mature-node business with little direct AI exposure. No judgment on which is the better buy is offered here.
Source: revenue/market-cap and all multiples are general-knowledge est. (cutoff ~early 2026), not live-verified; capex characterisation grounded in scan sub-sector 5 fab-cost note.
Where a company-level deep-dive would be most informative, factually:
Source: 500-stocks scan sub-sector 5 company list and supply/demand notes.
What was used:
/Users/ravf/projects/work/.claude/worktrees/sector-hub/research/investments/500-stocks/02-semiconductors.html.
This is the source for the company list (TSM, INTC, GFS, SSNLF, UMC), the "fab costs $20-40B / 3-4 years" figure, the
"allocated years ahead" and "CoWoS tightest bottleneck" claims, the "AI revenue growing 3x" note, and the ~50-60
EUV-systems/year figure./Users/ravf/projects/work/.claude/worktrees/sector-hub/research/investments/reports/research/industries/semiconductor-foundry.html
was NOT present at build time, so no V1 dated numbers could be folded in. If it exists elsewhere, its hard figures
should be merged on the next revision.Hard vs approximate: Treated as relatively hard (from the scan / well-known structure): the company list; that a fab costs $20-40B and takes 3-4 years; that leading-edge capacity is booked years ahead; that CoWoS advanced packaging is the tightest bottleneck; that only ~2-3 firms make leading-edge at scale; that ASML alone makes EUV tools at ~50-60/yr. Treated as approximate and NOT live-verified (all tagged est.): every dollar/percentage figure — global foundry revenue (~$150-170B), TSMC's ~60-70% total and ~90%+ leading-edge share, TSMC ~$90-100B revenue and ~$40B/yr capex, the ~$18-30k wafer prices, ~50-55% gross margins, the per-company revenue and market-cap numbers, and all price-to-revenue multiples. Confirm these against current 10-K/20-F filings and live quotes before relying on them. All forward demand-growth and oversupply-timing statements are forecasts, not contracted orders.
Source: as listed above. Live retrieval unavailable; estimate-tagged figures are not live-verified.