Snapshot — the group at a glance

FPGAs (field-programmable gate arrays) are chips whose internal logic can be rewired after manufacturing, sitting between general-purpose CPUs (flexible but slow for specialized tasks) and fixed-function ASICs (fast but frozen at the factory). The FPGA market generated roughly $10.7B in 2024 and is projected to reach $19.3B by 2030 at a 10.5% CAGR. Two players dominate: AMD (which acquired Xilinx in 2022 for $49B) holds roughly 70% market share, and Altera (spun out of Intel in September 2025 via an $8.75B Silver Lake deal) holds roughly 25–30%. Lattice Semiconductor is a distant third, focused on low- and mid-power FPGAs, with FY2025 revenue of $523M. The three tickers — AMD, INTC (49% Altera owner), and LSCC — give very different exposure: FPGA is a small minority of AMD's $34.6B revenue, a deconsolidated equity stake for Intel, and the entire business for Lattice. est.

FPGAs are growing at ~10% annually, driven by data-center companion roles (security boot, power sequencing, SmartNICs) and defense/industrial design starts. GPUs and custom ASICs dominate core AI training and inference workloads. The sub-sector is a duopoly (AMD + Altera) running on mature-to-mid-range foundry nodes with no acute shortage. Rising ASIC design costs ($100M+ for advanced nodes) push more low-volume applications toward FPGAs. Gross margins run 55–70% with modest capex, but none of the three tickers gives clean, isolated FPGA exposure.

The product & how money is made

An FPGA contains a grid of configurable logic blocks (small programmable circuits), interconnects (wires between them), and I/O pins. The customer writes a hardware description (in VHDL or Verilog), compiles it using the vendor's proprietary software tools, and loads the result onto the FPGA — effectively "programming" the hardware. The same physical chip can parse network packets in a SmartNIC today and run an image-processing pipeline tomorrow. The trade-off versus an ASIC: FPGAs are less power-efficient and slower clock-for-clock, but ship in months instead of years and skip the $100M+ mask set. est.

Money flows in two streams:

• Hardware (the FPGA chip itself): Sold per unit, priced from under $5 (Lattice's small FPGAs for IoT) to $10,000+ (AMD's Versal Premium adaptive SoCs for 5G and data centers). est. Lattice runs ~70% non-GAAP gross margin; Altera reported 55% in H1 2025. Vendors design the chip and have it manufactured at an outside foundry (TSMC for AMD and Lattice; Intel fabs and TSMC for Altera), so the model is asset-light.
• Software & IP (the design tools): Proprietary compilers, simulators, and pre-built IP blocks (verified circuit designs for common functions like PCIe controllers or Ethernet MACs). Only AMD and Altera possess full-stack FPGA software suites, per Altera's CEO. Software is typically bundled or sold as a subscription; it creates deep lock-in because porting a design means rewriting and re-verifying the entire logic in a different tool, which can cost months.

The key economic unit is the design start — the moment a customer commits to using a particular vendor's FPGA in a new product. Each design start leads to years of unit purchases once the customer's product enters production. Lattice reported design-win momentum at "record levels" in Q1 2026.

Source: Altera CEO (CRN, 2025); Lattice Q1 2026 earnings call (MarketBeat); AMD Q1 2026 press release.

Demand — how much the world will want this

Where FPGAs are used (end markets by demand driver)

• Data center & AI (~38% of Lattice Q1 2026 revenue): FPGAs serve as companion chips alongside GPUs, CPUs, and AI accelerators — handling platform management, secure boot (root of trust), power sequencing, I/O aggregation, and SmartNIC packet preprocessing. Lattice expects AI-related revenue to reach ~25% of its total in 2026, up from high-teens in 2025.
• Telecom & 5G: FPGAs process radio signals in base stations (beamforming, channel coding). Historically Altera/Intel's largest market; AMD's Versal RF Series also targets it. Telecom capex has been cyclically weak since 2023, depressing FPGA demand in this vertical.
• Aerospace & defense: Radar, electronic warfare, satellite systems. FPGAs are used because they can be updated after deployment and their logic can be radiation-hardened. Long product lifecycles (10–20 years), high margins. AMD's Versal AI Edge Series Gen 2 targets space-grade applications.
• Industrial, automotive & edge AI: Factory automation, robotics, ADAS sensor fusion, medical imaging. Lattice's Industrial & Embedded segment grew 21% sequentially in Q1 2026. Manufacturing PMI above 50 for four months was cited as a tailwind.

Contracted demand

• Lattice reported book-to-bill above 1.0 "for quite a few weeks" as of Q1 2025, and bookings extending "well into 2027" as of Q1 2026. contracted
• Altera H1 2025 revenue of $816M was up 16% YoY, implying recovering order flow after the 2023–2024 inventory correction. contracted

Forecast demand

• FPGA market projected at $11.7B in 2025 growing to $19.3B by 2030 (10.5% CAGR). High-end FPGAs grow fastest at 13.1% CAGR; embedded FPGA (eFPGA, where FPGA fabric is licensed as an IP block inside another chip) grows at 18.4% CAGR. Data center & computing is the fastest-growing vertical. est.
• Lattice targets exceeding a $1B annual revenue run rate by year-end 2026 (standalone, excluding the $1.65B AMI acquisition), and guides for 15–20% revenue growth in 2026. est.
• Altera CEO expects full-year 2025 revenue "reasonably higher" than 2024's $1.54B. The cost to build a custom 3nm ASIC now exceeds $100M, pushing more applications to stay on FPGAs. est.

Supply — how much can be made, and what limits it

FPGAs use mature-to-mid-range foundry nodes, not the bleeding-edge 3nm/2nm capacity that AI GPUs compete for:

• AMD (Xilinx): High-end Versal adaptive SoCs on TSMC 7nm. Older Zynq/Kintex UltraScale families on TSMC 16nm and 20nm. These nodes have ample capacity.
• Altera: Agilex 7 on Intel 7 (10nm-class) using Intel's own fabs. Newer Agilex 5 uses Intel 4 or TSMC. Post-separation, Altera has flexibility to use external foundries.
• Lattice: Nexus platform on Samsung 28nm FD-SOI; Nexus 2 on 16nm; Avant (mid-range) on an undisclosed advanced node. All avoid the CoWoS/HBM bottleneck entirely.

The 2021–2023 chip shortage, which stretched FPGA lead times to 52+ weeks, has fully unwound. Lattice's channel inventory dropped from ~3 months to below 2 months by Q2 2026, and the company called inventory "a non-issue going forward."

The real constraint is design tools, not wafers. Only AMD and Altera have full FPGA compiler suites — Altera's CEO called this the moat: "only two companies possess such comprehensive FPGA software." Building a competitive toolchain from scratch would take a decade+. est.

Source: Lattice Q1 2026 earnings (MarketBeat); Altera CEO interview (CRN, 2025); foundry node details from product pages.

The gap — demand vs supply

There is no acute supply shortage in FPGAs today. The 2021–2022 shortage has fully corrected, lead times have normalized, and channel inventories are lean. Demand is growing at ~10%, and mature foundry capacity can respond.

Pricing direction: ASPs are rising structurally — not from shortage, but from product mix shift. Customers are adopting higher-end FPGAs with more logic capacity and AI-adjacent features. Lattice called its ASP increases "very significant" stepping from pre-Nexus to Nexus to Avant families. The pricing power comes from product mix and design lock-in (switching costs), not scarcity.

Structural tailwind: ASIC design costs are rising sharply as process nodes shrink. A custom 3nm ASIC tape-out can cost $100M+, making FPGAs more economical for applications producing fewer than ~100,000 units. est.

Source: Lattice Q1 2026 earnings; Altera CEO (CRN); ASIC cost thresholds from industry estimates.

The players — who captures the money

Competitive dynamics: Altera's CEO stated that AMD's Xilinx unit is "being neglected" inside AMD because management prioritizes GPU/AI growth, and claims FPGA engineers at AMD are defecting to Altera. AMD's Salil Raje pushed back, calling Embedded "a strongly profitable engine for AMD" and pointing to FPGA-CPU-GPU integration as a differentiator. Design-start share over the next 2–3 years will show which is true.

Source: AMD Q1 2026 press release; Intel Q1 2026 press release; Lattice Q1 2026 earnings (MarketBeat); Altera CEO interview (CRN, 2025); Silver Lake press release (Altera, 2025).

The price of exposure

• AMD ($521, market cap $850B): At ~24.5x trailing sales on $34.6B FY2025 revenue. The Embedded segment ($3.45B, includes non-FPGA embedded CPUs) is roughly 4% of the market cap. The stock moves on GPUs (Instinct MI300/400) and CPUs (EPYC), not FPGAs. Q1 2026 FCF was $2.57B (a record), but virtually none is attributable to FPGAs in isolation. est.
• Intel ($108, market cap $542B): The 49% Altera stake was implied at ~$8.3B by the Silver Lake deal ($8.75B for 51%) — about 1.5% of Intel's current market cap. Intel's GAAP operating loss was $3.1B in Q1 2026 (driven by $4.1B in impairment charges). est.
• Lattice ($151, market cap $20.7B): The only pure-play. At ~36x trailing sales on $574M TTM revenue, forward P/E ~78x non-GAAP. If the company hits $1B revenue run rate by end-2026 at ~70% gross margin and 34% operating margin, that implies ~$340M annualized operating income, or ~61x forward operating income. Q1 2026 FCF was $39.7M (23% margin). The AMI acquisition ($1.65B, closing Q3 2026) adds ~$200M revenue and is funded by $1B cash + $650M in LSCC equity (~5.4M shares, ~4% dilution). Combined entity targets "roughly 40% free cash flow margin" per management. est.

FPGA revenue per dollar of market cap: Lattice gives $1 of FPGA revenue per $36 of market cap. AMD gives $1 of embedded-segment revenue (partly FPGA) per $246 of market cap. Intel's Altera stake gives $1 of Altera revenue per $65 of Intel market cap, through an unconsolidated 49% interest. est.

Source: Stock prices as of Jun 2, 2026 (StockAnalysis); AMD Q1 2026 press release; Intel Q1 2026 press release; Lattice Q1 2026 earnings; Silver Lake/Altera press release.

What to deep-dive next

• Lattice Semiconductor (LSCC) — the only pure-play FPGA equity. Key questions: (1) can it sustain 40%+ revenue growth as data-center companion-chip sockets proliferate, or does growth decelerate once the inventory recovery is complete? (2) What does the AMI acquisition do to the combined margin structure and competitive moat? (3) At ~36x sales, how much of the $1B run-rate target is already priced in?
• Altera (pre-IPO via INTC) — once Altera IPOs (~2028 est.), it becomes a direct FPGA pure-play. Monitor H2 2025 and 2026 revenue for share-gain evidence against AMD Xilinx. The CEO's claim that Xilinx talent is defecting is either the key competitive story or empty talk — design-start data over the next 4–8 quarters will show.
• AMD Embedded segment — if AMD breaks out FPGA-specific revenue or increases investment, the Embedded segment's trajectory would clarify whether FPGA share is being defended or ceded.

Sources & confidence

Grounded in primary sources (high confidence):

• FPGA market size ($10.74B 2024, $19.34B 2030, 10.5% CAGR) — MarketsandMarkets FPGA Market Report, 2025
• AMD Embedded segment: $3.454B FY2025, $873M Q1 2026 (+6% YoY) — AMD Q1 2026 press release and AMD FY2025 press release
• Altera: FY2024 revenue $1.54B, H1 2025 $816M (+16% YoY), 55% gross margin, Silver Lake 51% stake at $8.75B implied valuation — Altera/Silver Lake press release, CRN interview with Altera CEO (2025)
• Lattice: FY2025 $523M, Q1 2026 $171M (+42% YoY), 70% gross margin, Q2 2026 guide $175–195M, zero debt — Lattice Q1 2026 earnings (MarketBeat) and Lattice financials (MarketBeat)
• Intel deconsolidated Altera Sep 2025, 49% retained stake — Intel Q1 2026 press release
• AMD ~70% FPGA market share, Altera talent defections claim — CRN, Altera CEO interview
• Intel acquired Altera in 2015 for $16.7B; PSG trailing revenue $2.9B in Q2 2023 — CRN, Intel PSG spin-off details
• Stock prices and market caps as of Jun 2, 2026 — StockAnalysis (LSCC), StockAnalysis (AMD), StockAnalysis (INTC)

Directional estimates (lower confidence, tagged est.): AMD FPGA-specific percentage of Embedded revenue; ASIC design cost thresholds ($100M+ at 3nm); market share split (70/25-30/~5 for AMD/Altera/Lattice); foundry node assignments for specific FPGA families; Altera IPO timeline (~3 years). From industry knowledge and should be verified against current filings.