This group makes the small, unglamorous chips that let the expensive parts of an AI computer talk to each other fast enough. Inside an AI server, the GPUs (the graphics-style processors that do the actual AI math), the memory, and the network all need to move enormous streams of data between them. A signal sent at 100+ billion bits per second across a copper trace, a cable, or a backplane degrades and smears out. Retimers and SerDes (serializer/deserializer — the circuit that turns parallel data into one fast serial stream and back) clean up, re-time, and re-launch that signal so it arrives intact. Related parts include PCIe/CXL switches (PCIe and CXL are the standard high-speed links that connect processors to memory and accelerators inside a server) and "active electrical cables" (cables with a chip inside that boosts the signal). The buyers are the companies building AI data centers — Nvidia and AMD systems, the big cloud operators (Amazon, Microsoft, Google, Meta), and the server makers (Dell, Supermicro). The focused, single-product names here are Astera Labs (ALAB) and Credo (CRDO); the large diversified suppliers are Broadcom (AVGO) and Marvell (MRVL).
Two facts an owner is weighing. First, on the product: the scan rates AI demand for this category "very strong" and supply only "moderate"-ly constrained — demand is rising faster than the overall server count because the number of high-speed links per AI server keeps climbing as clusters grow, while supply is gated not by raw materials but by the small number of teams that can design working 100G+ SerDes and by access to leading-edge contract fabs (chip factories). Second, on the price of exposure: the two focused names (ALAB, CRDO) have traded at a high multiple of their current sales, so a buyer pays many years of today's revenue up front; the two diversified names (AVGO, MRVL) trade at a lower multiple per dollar of total company sales, but only a fraction of those sales comes from this specific product. Both the multiples and the market-size figures below are approximate and not live-verified.
Source: 500-stocks scan, "Networking & Interconnect Chips" section (/Users/ravf/projects/work/.claude/worktrees/sector-hub/research/investments/500-stocks/02-semiconductors.html, lines 980-1020); market-size, growth, and multiple figures from general knowledge, not live-verified.
The product is a signal-integrity chip — a piece of silicon whose only job is to keep a very fast data stream readable as it travels. Three flavors matter here:
How the cash actually comes in: (1) selling the physical chip per unit — the dominant model for ALAB and CRDO; a server or system may contain several to dozens of these chips, each priced roughly from a few dollars to tens of dollars est. (per-unit pricing not live-verified); (2) licensing the SerDes IP — an upfront license fee plus a royalty (a small cut of each chip the customer ships using the design) — relevant for MRVL and for IP-centric vendors; (3) bundling connectivity into a larger custom-chip or networking deal — how AVGO and MRVL mostly monetize it. The unit of demand to track is "high-speed connectivity chips per AI server," and that number rises as link speeds and link counts grow.
Source: 500-stocks scan section (lines 988-1001); product/business-model description and per-unit pricing from general knowledge, not live-verified.
The direction of demand is mechanical, not speculative: every additional GPU in a cluster adds links, and the data each link carries keeps rising. The scan section states it plainly — networking "scales super-linearly with GPU count: a 100K-GPU cluster needs a massive fabric," and the industry shift to 800G and 1.6T (800 billion / 1.6 trillion bits per second) Ethernet "drives huge switch/transceiver demand." Retimers and SerDes sit underneath all of that: faster links degrade faster, so they need more re-timing, not less.
Who the buyers are: the AI-system builders (Nvidia, AMD), the hyperscale cloud operators (the largest cloud providers — Amazon, Microsoft, Google, Meta — many of which design their own accelerators and servers), and the contract server/box makers (Dell, Supermicro, and switch vendors such as Arista). These are concentrated, deep-pocketed buyers spending heavily on capex (capital expenditure — money spent on long-lived equipment like data centers and servers).
Current demand (grounded direction): the scan rates the AI demand driver as "Very strong." Forward demand (forecast): reasoning from the premise that AGI-scale compute build-out continues, the unit count per server rises on two axes at once — more accelerators per rack and more re-timing per link as speeds go from 400G to 800G to 1.6T. On that reasoning, this chip category would grow faster than server units themselves. The dollar size below is a forecast and approximate.
✓ VERIFIED — the following figures were confirmed from primary sources after initial publication:
Source: 500-stocks scan section (lines 998-1001) for demand direction and the 800G/1.6T driver; dollar/TAM/growth figures from general knowledge, not live-verified; AGI-build-out premise per project worldview.
Unlike memory chips or advanced packaging, the binding constraint here is, per the scan, not a scarce physical input or a single factory line. The scan rates supply as only "Moderate"-ly constrained, noting that "high-speed SerDes and optical components are tight" and that "custom AI networking ASICs compete for leading-edge fab capacity." The constraints it points to are:
Market-share structure (who controls supply): the scan lists the relevant suppliers as Broadcom (AVGO), Marvell (MRVL), and the focused names Credo (CRDO) and Astera Labs (ALAB), plus Alphawave (AWSE). Broadcom and Marvell are the largest, with the broadest SerDes IP and custom-chip franchises; Astera Labs is focused on PCIe/CXL connectivity (retimers, fabric switches); Credo is focused on active electrical cables and SerDes chiplets. The scan also flags that Nvidia (Spectrum-X, ConnectX) holds significant share in the broader AI-networking layer — relevant because Nvidia can absorb some connectivity in-house, which is a competitive factor for the merchant (third-party) suppliers.
Source: 500-stocks scan section (lines 1000, 1004-1017) for constraint level, fab competition, and supplier list; design-difficulty and foundry-dependence framing from general knowledge, not live-verified.
Putting the two sides together: per the scan, demand is rising faster than the number of servers (more links, faster links), while supply is gated by scarce design talent and shared fab capacity rather than expandable on command. On those labels the product runs tighter than a typical chip but looser than memory or CoWoS packaging — the scan rates demand "very strong" and supply only "moderate." The degree of tightness is greatest for the hardest, newest speeds (224G-class SerDes, 800G/1.6T-era parts) and least for older, commoditized speeds where more vendors can compete.
What could move it toward oversupply: this is silicon design, not a power plant or a mine, so there is no permanent physical scarcity. Once a hard SerDes generation is solved, the design can be replicated and licensed, more vendors qualify, and pricing on that generation tends to erode. The tightness is therefore per-generation: each speed node is tight at launch and loosens as it ages. A broad oversupply would more likely come from an AI-capex slowdown (fewer servers ordered) than from a sudden flood of new supply. Timing of either is unknown and is a forecast.
| Signal | What it suggests | Confidence |
|---|---|---|
| Demand rated "very strong"; links-per-server rising | Demand growing faster than server count | Grounded (scan) |
| Supply rated "moderate"; SerDes design scarce | Product is tight, especially newest speeds | Grounded (scan) |
| Pricing / lead-time / utilization specifics | Would quantify the degree of tightness | Not live-verified est. |
| When could it flip to oversupply? | Per-generation as designs commoditize, or on an AI-capex pullback (timing unknown) | Forecast forecast |
Source: 500-stocks scan section (lines 998-1001) for the demand-vs-supply read; oversupply-timing reasoning is a forecast, not live-verified.
The distinction for an owner: a focused name (almost all of its money comes from this product, so exposure and risk are both concentrated) versus a diversified company (this product is a small, faster-growing slice of a much larger business). All revenue-share and size figures below are approximate and not live-verified.
| Company | What it makes here | Exposure to THIS product | Rough size est. | Position |
|---|---|---|---|---|
| Astera Labs (ALAB) | PCIe/CXL retimers, fabric switches, connectivity modules | Focused (~all revenue) | Mid-cap; revenue on the order of ~$1B run-rate est. | Focused on PCIe/CXL connectivity; design-ins with AI-system builders |
| Credo (CRDO) | Active electrical cables (AECs), SerDes chiplets, line-card retimers | Focused (~all revenue) | Mid-cap; revenue smaller than ALAB est. | Focused on AECs; in-rack copper links with hyperscalers |
| Marvell (MRVL) | SerDes IP, custom AI silicon, optical DSPs, switching | Diversified — connectivity is one of several large segments | Large-cap | Broad SerDes IP; large custom-chip franchise with hyperscalers |
| Broadcom (AVGO) | SerDes IP, switch/router chips, custom AI accelerators, much more | Diversified — this is a small slice of a very large company | Mega-cap | Broad connectivity IP at scale; large networking-chip business |
| Alphawave (AWSE) | SerDes/connectivity IP and chiplets (also listed in scan) | Focused IP vendor | Small-cap est. | SerDes IP supplier; smaller scale |
Competitive factor to keep in view: the scan notes Nvidia's strong position in AI networking (Spectrum-X, ConnectX). To the extent Nvidia and the hyperscalers absorb connectivity in-house, that limits the merchant suppliers' addressable share — a factor that bears more on the focused names than on the diversified ones, since the focused names have no other segment to offset it.
Source: 500-stocks scan section (lines 1004-1017) for the supplier list and Nvidia position; segment-mix, revenue, and market-cap descriptors from general knowledge, not live-verified.
Translating valuation into plain money — "how many dollars of market value am I paying for each $1 of this year's sales?" — the two camps differ. (All multiples below are approximate, order-of-magnitude, and not live-verified.)
Money-in / money-out shape: this is a capital-light business. These companies are "fabless" — they design chips and pay contract foundries (TSMC) to manufacture, so they do not carry the enormous factory capex of a foundry or a data-center operator. That means, at scale, a high share of revenue can convert to EBITDA (earnings before interest, tax, depreciation and amortization — a rough proxy for operating cash generation) and to owner cash. The diversified names (AVGO in particular) already generate large owner cash today. The focused names are growing faster but are earlier-stage, so more of today's market value reflects forecast future cash than cash currently produced. Stated as the owner's choice without a verdict: one option pays a high multiple for concentrated, capital-light, fast-growing but not-yet-mature cash flow (focused names); the other pays a lower multiple per dollar of mature cash but gets this product only as a minority slice (diversified names).
Source: valuation multiples and the fabless/capital-light characterization from general knowledge, not live-verified; business model corroborated by the 500-stocks scan section.
Where a company-level deep-dive would add the most factual information:
Source: 500-stocks scan section (player list and Nvidia position); focused-vs-diversified framing from this sheet's analysis. Not a recommendation.
What was used:
Hard vs approximate:
An owner can treat the structural facts (per the scan: tight product, capital-light fabless economics, focused-vs-diversified split) as grounded, and re-pull live revenue, backlog, diluted share count, and current multiples for any of the four names before acting on the numbers.
Source: as listed above. Live web retrieval was unavailable at build time; figures not in the provided files are general-knowledge estimates and not live-verified.